Diode gate



March 30, 1954 J. R. HARRIS DIODE GATE Filed April 28, 1952 2 Sheets-Sheet 1 R m Ms @M m S TERM/N41.

52 POTENTIAL TERMINAL 6/ POTENTIAL TIME //v VEN TOR J. R. HA RIP/S ATTORNEY March 30, 1 54 J. R. HARRIS 2,673,936

DIODE GATE Filed April 28, 1952 2 Sheets-Sheet 2 F IG. 3 7/) 72) 73 74) 75w PULSE E/NARY w BINARY BINARY C\ BINARY GENE/MIDI? cou/vrm *c'owvrm co'u/vrER COUNTER I l \I I 1 79 A V ,4 a ,4 a A a LOAD a0 0am I as NW-l V v v W1] 86 ll a l w TO OTHER MATRIX GATES INVENTOR I'l F J. RHARR/S ATTORNEY Patented Mar. 30, 1954 DIODE GATE James R. Harris, Dover, N; J assignor to Bell Telephone Laboratories, Incorporated, New York, N. Y., a corporation of New York Application April 28, 1952, Serial No. 284,769

7 Claims. 1

This invention relates to electronic gating cirsuits and more particularly to the reduction of direct current power drain in such circuits.

The invention is described below as relating to a class of gates commonly called diode gates or switches. This type of gate has assumed increased importance due to the development of improved semiconductor diodes, such as germanium crystalcat whisker diodes or p-n junction diodes, formed, for example, from germanium or silicon. Such devices are essentially asymmetrically conducting impedance elements having a low forward impedance and a high, although not infinite, reverse impedance. The small size, low operating temperature, and high speed switching possibilities of these devices make them relatively ideal for packaged switching circuits which may be employed, for example, in either large or small scale digital computing devices. With packaged circuits particularly, the problem of direct current power drain becomes a major consideration, and even relatively small savings in power are much to be desired.

A principal object of the invention, therefore, is to decrease the direct current power drain in electronic gating circuits.

A more particular object of the invention is to decrease the peak power drain imposed on the control voltage source by the gating circuit itself.

A further object is to permit the use of a control voltage source having low power output capability and low direct current power drain.

An illustrative embodiment of the invention described in more detail below comprises a plurality of semiconductor diodes connected by like electrodes to a common junction; a direct current bias is also applied to the junction. A load circuit is connected to one ofthe diodes, and con trol voltages are applied to the remaining diodes. The control voltages are derived from the stages of a binary counter which is triggered in a regular manner. Following each stepping of the counter, a elockpulse is applied to the junction mentioned above. If any of the diodes is in its low resistance condition, i. e., if it is in the disabling condition, the clock pulse will be bypassed through the disabled diodes to ground; the direct current bias holds the output diode OFF under such a condition. If all of the control voltages of the proper polarity to bias their associated. control diodes in their high resistance condition, 1. e., if all control diodes are in the enabling condition, the clock pulse will overcome the bias on the output diode and pass to the load circuit.

Were the circuits contemplated by the present invention not employed, control voltage sources in the disabling condition would be subjected to an undesirable power drain upon the occurrence of a clock pulse. In accordance with the principles of the invention, however, a shunt condenser is connected to the control terminal of each control diode. These condensers are charged slowly by the control voltage sources, following each stopping of the binary counter, through a properly proportioned resistor.

The clock pulses are delayed a sufficient time interval following each stepping of the counter to permit the condensers to charge substantially to the full control voltage. When a clock pulse passes through a control diode, it in effect "sees a low impedance path to ground through the condenser which is discharged partially by the clock pulse. The condensers, therefore, effectively isolate the control voltage sources from the clock pulses and substantially eliminate the peak power drain which would otherwise be caused by these pulses. A feature of the invention is that control sources (e. g., binary counter stages), which have high output resistance, low power output'capability, and correspondingly low direct current power drain may be used.

Other objects and features of the invention will be understood from a consideration of the following detailed description when read in accordance with the attached drawings, in which:

Fig. 1 is a circuit diagram of a diode gate emplaying principles of the present invention;

Fig. 2 is a timing diagram illustrative of the operation of the circuit of Fig. 1; and

Fig. 3 is a circuit diagram of a program generator which also employs principles of the present invention.

The circuit illustrated in Fig. 1 includes a pulsed diode gate I!) which is connected to reoognize a specific count of a two-stage binary counter comprising the counter stages 1 l and I2. The gate It will deliver a pulse to the load l3 upon a recognition of this specific count. The gate [0 comprisesv the p-n junction diodes l4, l5, and it connected by like electrodes to a junction designated I1. Diodes of this type are described in Patent 2,402,662 to R. S. Ohl, dated June 25, 1946. The diodes l4 and I5 are called control diodes, and the diode I6 is termed the output diode, since the desired pulse must pass through this latter diode. to reach the load l3. The gate as thusfar described is similar to a switching type gate described in a copending application of L... W. Hussey, Serial No; 198,688, filed December 1, 1950, which issued as Patent 2,636,133 on April 21, 1953. A direct current bias is applied to the junction ll by the battery It through the resistor is. The bias voltage applied to the junction H by the battery IS in the absence of pulse P2 is so chosen as to be always slightly more positive than the most positive potential which will exist at a control input lead, i. e., at the terminals 2| and 22 for the disabling state. A further bias is applied to the output diode It by the battery 23 through the resistor 24. The purpose of this bias is to keep the output diode l6 non-conducting except when the control voltages are such as to enable the gate and pulse P2 to be applied. This bias is selected such that the voltage at junction H3 is slightly more positive than the most positive voltage which appears at junction I1 during input pulse P2 when the control voltages are set to disable the gate.

The operation of the gate shown in Fig. l differs from the gate described in the Hussey application mentioned above in several respects. Whereas the gate described in the l-lussey application delivers current from a direct current source (connected to junction I'I) upon a proper coincidence of control voltages, the biasing voltages of the gate shown in Fig. l are so proportioned that the voltage at the junction I! is insufiicient to overcome the reverse bias on the output diode l6 even when all of the control voltages are enabling. As a substitute for the current delivered by the direct current source, a short pulse is applied to the junction 11 by way of the transformer 25 and will, if the control voltages are all enabling, overcome the reverse bias of the output diode l6 and pass to the load. By enabling control voltages is meant control voltages which tend to enable the gate to permit a pulse to pass to the load; in Fig. 1, the gate will be enabled if both control voltages are positive (relatively speaking) so as to bias the control diodes in their high resistance condition. Conversely, "disabling voltages are those which disable the gate; in Fig. 1, the more negative of the two negative control voltages is the disabling voltage.

The gating circuit it of Fig. 1 can be expanded to accommodate more controls by adding further control diodes connected to junction 11. P-N junction diodes are employed in the illustrative embodiment because of their relatively high reverse impedance which permits the addition of more controls without unduly loading the pulse input supply, to be described below.

The operation of the circuit as thus far described, and omitting for the present the modifications in accordance with the present invention, is as follows. A pulse generator 26 applies a pulse P1 through the condenser 21 to the first stage I l of the binary counter. Counter stage H is a bistable circuit, described in more detail below, which will assume its opposite stable state upon the application of a trigger pulse. The stage H is coupled to the stage i2 through the condenser 28, and the two. stages will count in binary fashion in a well-known manner, the two stages being capable of counting up to four. The same pulse which triggers the binary counter is delayed by the delay circuit 29 and, as pulse P2, is applied to the transformer 25 and thence to the junction [1. The delay provided by the delay circuit 29, among other things, permits the binary counter to settle down. If at this time the voltages at terminals 2! and 22 are both enabling, the control diodes l4 and will be biased off,

and the delayed pulse applied to the junction [1 will pass to the load [3. However, if either or both control voltages are disabling, the positive pulse will be blocked and will not pass to the load.

For the present, assume that at each pair of counter stage output terminals 5I-52 and Bl-GZ, there will be available two potentials, both negative, with one more negative than the other by an appreciable amount. These potentials are determined by the voltage of source 31 and the voltage drop across resistors 36 and 36. The source 31 may be common to both stages H and I2.

As mentioned above, if the potentials of both terminals 2i and 22 are positive, 1. e., the less negative of their two values, the junction I! will rise to the potential of the battery l8, since both diodes l4 and I5 will be biased in their high resistance conditions by positive control voltages. This potential is sufiiciently negative with respect to the voltage at junction 10 due to battery 23 that the diode I6 will remain in its high resistance condition and block current from battery ill but will pass a positive pulse of sufiicient amplitude applied to the junction by way of transformer 25.

Assume, however, that the control terminal 2! is at the more negative control potential and that a positive pulse P2 is impressed on the transformer 25. Junction 11 will be more positive than terminal 2! so that the diode l4 will be a low resistance (e. g., a few hundred ohms). It is necessary that the source as seen by the control terminal of diode ll be a low impedance;

.' otherwise pulse P2 would develop positive voltage on junction I! such as to transmit a spurious pulse to the load 13 through output diode H5 or else the voltage of battery 23 would have to be increased, thus reducing the signal available at the load I3. It is desirable for a control diode which is set to disable the gate to become a low impedance without delay when the pulse P2 appears. It has been found that this is facilitated with certain diodes if there has been a small forward current in the diode prior to the applica tion of the large forward current due to pulse P2. This is the reason for choosing the voltage of battery [8 such that even in the absence of pulse P2, junction 11 is more positive than the disabling control voltage.

If the control potential at terminal 52 were applied directly to the electrode of the diode I4 remote from the junction 11, i. e., if the condenser 63 and resistor 64 were omitted, the relatively heavy current due to pulse P2 would flow in terminal 52 of the binary counter stage i l (control voltage source) when control diode M is in its low resistance state. Thus, the stage II would have to be capable of passing these pulse currents in terminal 52 without changing falsely to its other state. This may be a serious disadvantage. Also, the impedance seen looking into terminal 52 of stage I i would have to be relatively low to give proper and eflicient operation of the gate. This last requirement means (assuming that the control voltages required by the gate are fixed) that the source stage I I would have to draw relatively larger direct current power, and the electronic devices 3! would dissipate relatively large direct current power. The requirements would be even more stringent if more than one control diode were fed from the same source.

The same, of course, would be true for the source terminal Bl associated with counter stage 2 were the condenser 65 and resistor 65 omitted.

In accordance with principles of the present invention, "lioweverfshunt'condensers" 5.3 *and" 65' are connected to the controrelectrodes of the'control diodes i Iand 15. These ci'anden'sers are charged, through properly proportioned "resistors 64 and (to the potentials" existing at output terminals 52 and filfie'spectivelyf Thetini'ec'onstants of these RC combinations are fairly large sothat when the control'potential at'terminal 52 or El changes, its associated condenser'charges fairly slowly to "the potential of'the control voltage. thereby requiringbut a smallcharging current and greatly reducing the peak'loadon the counter stages. Delay circuit 29 provides'suificient delay for the condensers 6 3- and 65 to charge substantially to the fulfpote'ntial of their associated con trol terminals" 2 1 and 22 before the delayed pulse P2 is applied wine junction I] of the gate 10; If the'del'aypulse-Pz should find either'control dio'de'set to disable, ityvould then'merely discharge its associated shunt condensers 63 and 65 and would not drain appreciable" current from the counter stages.

The condensers 63 and 6d provide a very low impedance'shunt path to the input pulses P2 when the" associated 'contr'ol'diode is conducting, thus allowing" e'fficierit' operation of the gate. The condensers 63 and 65 in combination with resistors and 66 revent the new of large currents in the outputterminals 52'an'd SI of sources'li and 12, thus protecting sources and l2 from the relatively large'current from pulse P2. Thus, the invention permilts the use of source stages l I and [2' having high impedance,'low direct current power 'drainfand lowpower' output capabilityio r,conversely," permits much higher pulse current in load"l3'with'given sources H and i2:

' The condensersfii andBS and't'h'e resistors 64 and 56 also perform other functions that'are'pa'rticularlyuseful if there is"appreciable shunt capacity the impedance of iodes I4, I5 and i 5. They-prevent any" sharp wave fronts from a binary counter, when reversing, from'being' transrinit'ted 'to' another" binary counter or to the load The illustrative binary counter stage I I is similar to theone shownand described in a copeniding application of Anderson and R. L. Trent, Se1ialN64246Q833, filed September 15, 1951, which issued as Patent 2,622,212 on December 16, 1952.

circuit'ofthe type shown and described in "a 'copendingapplication 'of.R."L; Trent; Serial No. 223,522, filed April '28, 1951, which issued as Patent 2,622,211 on December'lfi; 1952., Looking at the left half of the counter for example, this trigger circuit comprises the transistor 3 I "having an emitter electrode 32'," a collector electrode 33, and ab'as electrode 34; "A relatively large resistor 35 is connected to the base electrode and 46, to ground, and returning to base electrode 34. h o h the c ,qcinb'inc O a t grounded source; resistor 39,- and diode.- liil, and theresistorcili f the negative. emitter current regi'om the diodetdflfbiasedbycurrent fromsourceilwhich I Each halfof *thecounter is'a transistor trigger a high impedance.

flows through resistor 39, is a .low impedance and eifectively switchesthe large .base resistance provided by resistor 39'outjof the circuit. When the emitter current becomes positive, however, the diode becomes a high impedance and effectively switches the resistor 39 into the base circuit to provide additional regenerative feedback which gives rise to the trigger properties of the circuit. The resistor 35 insures that there will be suincient resistance in the base circuit to provide enough regeneration to promote instability as soon as the emitter current becomes positive, even though the diode 40 may not reverse until some positive emitter current is reached. The load line resistor 46 is proportioned to give the circuit two stable operating points, one in the negative emitter current region characterized by low oollector'current and a collector voltage (and hence terminal 5! voltage) of approximately -30 volts, and the other one inthe positive emitter current region characterized by high collector current and a collector voltage of approximately -10 volts.

The right-hand trigger circuit is similar in all respects, and the'same numbers with the addition ofiprimes are used to indicate similar elements. The two trigger circuits'are interconnected by the resistor-condenser couplings 55 and 55 which cross-couple the collector and base electrodes, and by the common load line resistor 45. When one trigger circuit is switched on, the other will be switchedtoff by the cross-connections just described. The diodes and 45" and the condenser 56 cooperate to promote trigger sensitivity. These diodes raise the emitter potential of the off unit to a potential quite near the trigger point but have substantially no effect on the emitter potential of the on unit. Resistors 5'! and 51' also promote trigger sensitivity'as well as reliablity. Condenser 5t aids in commutation and insures that once the trigger circuits start to reverse states, they will continue in that direction until theyreach the opposite stable state;

' Trigger pulses are applied to the base electrodes as and 34 throughthe steering diodes 5S Due to the difierences of'potential between the base electrode of the on unit and the base of the off unit and aided if necessary by bias from the source 59, the diode connected to the base of the on unit will be in its low impedance condition while the other diode will be Trigger pulses are therefore "steered to the base electrode of the on unit. These pulses, being positive, tend to turn the on unit off and, being passed by the low en1itter to base internal resistance of the on transister through condenser to the emitter of the oil unit, tend to turn thebfi unit on. The cross-couplings 55 and 5E. increasethese tendencies which become cumulative so that the trigger circuits rapidly reverse states. The poten tials at terminals 5| and 52 also reverse, one assuming apotential of -10 volts (the on unit) and the other -30 volts. Output may be taken from either of these terminals.

The counter stage i2 is similar to the stage i! just described, Count-input pulses are applied to an input terminal es similar to the input terminal E53 of. stage ii. These pulses are not derived directly from the generator 25, however, but are derived from. the preceding stage. A positive going pulse will-appear at output terminal 5! each time the left-hand trigger oi suit of this stage triggers fro'm fofi to on, and it is this pulse which triggers the next. stage. Itrnaybe seen that the s econd stagecountsat a rate one half that of the first stage; if succeeding stages were added, they, too, would each reverse or count at a rate of one half the rate of the next preceding stage.

The output terminals 6! produce voltages similar to those at terminals and 52 although at a different rate. Output control voltages may be derived from either terminal of each pair, depending on the time in the cycle it is desired to energize the gate H1. By way of example, and assuming the left-hand trigger circuits of each stage to be ON upon the receipt of the initial trigger pulse from the generator 26, the potentials at terminals 52 and i i are illustrated in the timing diagram of Fig. 2; occurrence times of the trigger pulses are illustrated by P1 and the delayed pulses which are applied to the gate In by P2.

Pulse Pl at time h reverses terminal possible potentials volts in the example given) designated positive herein; terminal Si is already positive by the initial assumption and is undisturbed. The delayed pulse P2 in the time interval 151 to in will therefore find the gate completely enabled and will pass to the load l3. Pulse P1 at time t2 will reverse counter stage H which will in turn reverse counter stage I2 so that the pulse P2 in the time interval is to ts will find the gate disabled and will not be transmitted to the load. From a study of the timing diagram, it may be seen that the gate It] will be enabled but one time interval out of each successive four, and if n is assumed to be the beginning of a frame, the gate will be enabled for the first pulse P2 in each frame.

If, for example, a third control arm is added to the gate H1 and a third counter stage is added to the counter to produce control voltages for this added control arm, it may be seen that, since the counter thus expanded can count to 2 or 8, the modified gate, by selection of a proper control ter-- minal from each counter stage, could recognize any one count of an eight-pulse frame; for example, it could deliver a pulse to the load is upon the and 62 of stage l2 stage II so that occurrence of a second or fifth or seventh, etc.,

count pulse, as desired. As is known, a unique combination of enabling control terminals is available for any desired count, provided the has a sufficient number of stages; this combination will not enable count.

Fig. 3 illustrates an application of principles of the invention to a program generator. Fundamentally, the program generator consists of four binary counters, pulsed lar to those illustrated in Fig. 1, and a master cloclz. The master clock is the pulse generator H which may, for example, comprise a crystal controlled oscillator which delivers count pulses at the fundamental programming rate to the first counter stage 12. The counter, including stages 12-?5 will thus count in a regular manner at this fundamental rate, completing a cycle of operation every 2 or 16, pulses.

A fundamental property of binary counters which is used to obtain recognitions of specific counts is the condition that a unique combination of counter stage output potentials corresponds to each specific count. The matrix gates y it, ii, 13, are therefore connected to the counter stage outputs in such fashionthat-when a specific count desired to be recognized is attained, the gate will respond, producing an output in the form of a pulse which is delivered to- 52 assumes the less negative of its two the gate at any other diode matrix gates simi- 8., the load 19.. At all other conditions of the counter outputs, at least one of the control diodes prevents any response.

Each counter stage has two output leads. The lead which is chosen arbitrarily to define whether a stage is on (10 volts) or off (30 volts) is designated B in Fig. 3. The output lead (of the same stage) designated Awill always have the opposite condition. A control diode connection to a matrix gate is made to the particular binary counter output lead which will be in the -10 volt condition at the desired count. The control diode connections of matrix gate 16 are made to output leads ABAA of the counter stages 12-15, respectively; this gate will therefore deliver a pulse to the load 19 at a count of 2. Matrix gate 11 will deliver a pulse to the load at a count of Sand gate 18 at a count of 10. The pulses applied to the load 19 may, for example, be programming pulses which control the timing of desired operations in the load circuit. The counter may easily be translated into a decade type by utilizing the pulse delivered by matrix gate 18 upon a count of 10 to reset each of the counter stages 12-15 to their starting condition; interstage gates, disabled during the resetting operation, would assist in performing this function.

The output from the basic frequency pulse generator I! is impressed upon the count lead C of the first binary counter stage 12 and also upon all of the matrix gates through a delay circuit This delay functions similarly to the delay 29 in Fig. 1 and permits the binary counter stages to operate and the shunt storage condensers associated with each control diode to be charged. When all of the control inputs to a particular matrix gate are enabled, the delayed pulse is transmitted to the load.

The matrix gates shown in Fig. 3 have been bodifled from those illustrated in Fig. 1 in several respects. First, bias is applied to each gate from source 81 over lead 82 through choke coils 83 shunted by diodes 84. These provide a high alternating current impedance to the delayed input pulses and a low direct current impedance bias feed. The shunt diodes 8-4 suppress any re verse kick produced by, the-retard coils, The small series resistors 85 inserted between the control diodes and the retard coils among other things limit the pulse current in the disabling condition. The shunt diodes 86 across the biasing resistors 81 associated with-the output diodes suppress any negative pulses which may leak through the output diode due to delayed switchoff or low reverse impedance.

Although the invention has been described as relating to specific embodiments, it should be understood that the invention is not limited to the apparatus or circuital arrangements specifically described, since other embodiments and modifications will readily occur to one skilled in the art without departing from the invention.

By way of example, the control voltage sources need not be interdependent as illustrated but could operate independently at random or in responsejto either local or remote controlling circuits.

What is claimed is:

1. An electronic gate comprising a plurality of two-terminal asymmetrically conducting impedance-elements each having a first terminal connected to a junction, a source of direct current I connected to. said junction, a source of pulses,

means for-applying said pulses to said'iunction means for derivin an output from the second terminal of one of said asymmetrical impedance elements, a plurality of control potential sources, one for each of the remaining asymmetrical impedance elements, said control potentials each having either a first or a second. value, and means comprising a series resistor and a shunt capacitor for uniquely applying said control potentials to the second terminals of said remaining asymmetrical impedance elements.

2. In combination, a binary counter having a plurality of tandem stages, an electronic gate having a plurality of control means, a source of pulses connected to the input of said gate, a load circuit connected to the output of said gate, a storage capacitor connected to each of said control means, and means for charging each of said capacitors to a potential derived from one of said tandem stages.

3. In combination, an electronic gatin circuit having an input, an output, and a plurality of shunt control arms each including an asymmetrically conducting impedance element, a shunt capacitor connected to each of said control arms, a binary counter having a plurality of tandem stages, means for charging each of said capacitors to a potential derived from one of said tandem stages comprising a resistor connecting each of said control arms to an output terminal of one of said tandem stages, means for applying countin pulses to said binary counter, means for applying a pulse to the input of said gate after the application of each counting pulse to said binary counter, said resistors and capacitors proportioned to utilize the major portion of the interval between each pair of consecutive counting pulses for charging said capacitors, and means for delayin the application of said pulses to the input of said sate by an amount following the preceding counting pulses sufficient to permit said capacitors to be substantially completely charged.

4. In combination, a source of pulses, a load, and means for gating said pulse to said load .10 only upon a coincidence of predetermined conditions comprising a first two-terminal asymmetrical impedance element connecting said source to said load, a plurality of two-terminal asymmetrical impedance elements connected to a junction between said source and said load and each poled, with respect to said junction, similarly to said asymmetrical impedance element, a plurality of control voltage sources rei sponsive to said conditions, a capacitor connected to the terminal of each of said asymmetrical elements re; from said junction, a resistor connected to each of capacitors, and means for charging each of capacitors through its associated resistors to a voltage determined by one of said control voltage sources,

5. The combination in accordance with claim 4 and means for applying a relatively large forward bias to each of said plurality of asymmetrical devices in response to the one of said predetermined conditions to which its associated control voltage source responds, and means for applying a relatively small forward bias to each of said plurality of asymmetrical devices in response to a condition other than the said predetermin d condition to which its associated control voltage source responds and in the absence or" said pulses.

6. The combination in accordance with claim 4 and means for applyin a reverse bias to said first asymmetrical device in the absence of said pulses.

7. The combination in accordance with claim 6 wherein the said reverse bias is proportioned to be reversed by said pulses in response to said coincidence of predetermined conditions.

JAMES R. HARRIS.

References Cited in the file of this patent UNITED STATES PATENTS Number Name Date 2,541,039 Cole Feb. 13, 1951 2,556,200 Lesti June 12, 1951 

